TMS570LS3137 datasheet(140/159 Pages) TI

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TMS570LS3137

SPNS162.

– SEPTEMBER 2011

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5.10 Multi-Buffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.

Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display

drivers, and analog-to-digital converters.

5.10.1 Features

Both Standard and MibSPI modules have the following features:

•

16-bit shift register

•

Receive buffer register

•

8-bit baud clock generator, supports max up to 20Mhz baud rate

•

SPICLK can be internally-generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

•

SPI I/Os not used in the communication can be used as digital input/output signals

Table 5-19. MibSPI/SPI Configurations

MibSPIx/SPIx

I/Os

MibSPI1

MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA

MibSPI3

MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA

MibSPI5

MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA

SPI2

SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA

SPI4

SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA

5.10.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a

16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each.

5.10.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event

and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low

level at a selectable trigger source. For example, up to 15 trigger sources are available which can be

utilized by each transfer group. These trigger options are listed in Table 5-20, Section 5.10.3.2 and

Section 5.10.3.3 for MibSPI1, MibSPi3 and MibSPI5 respectively.

140

Peripheral Information and Electrical Specifications

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