910GL datasheet(119/426 Pages) INTEL

119 / 426 page

DMIBAR Registers—Direct Media Interface (DMI) RCRB

Datasheet

119

7.1.6

DMIVC0RCTL0—DMI VC0 Resource Control

MMIO Range:

DMIBAR

Address Offset:

014h

Default Value:

8000007Fh

Access:

R/W, RO

Size:

32 bits

This register controls the resources associated with PCI Express Virtual Channel 0.

Bit

Access &

Default

Description

Virtual Channel Enable (EN): Enables the VC when set. Disables the VC when

cleared.

30:27

Reserved

26:24

000b

Virtual Channel Identifier (ID): Indicates the ID to use for this virtual channel.

23:20

Reserved

19:17

R/W

Port Arbitration Select (PAS): Indicates which port table is being programmed.

The root complex takes no action on this setting since the arbitration is fixed and

there is no arbitration table.

Load Port Arbitration Table (LAT): The root complex does not implement an

arbitration table for this virtual channel.

15:8

Reserved

7:1

R/W

7Fh

Transaction Class / Virtual Channel Map (TVM): This field indicates which

transaction classes are mapped to this virtual channel. When a bit is set, this

transaction class is mapped to the virtual channel.

Reserved

910GL Folha de dados(PDF) 119 Page - Intel Corporation

910GL Folha de dados(HTML) 119 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL