SPMCK16Z4MPV20 datasheet(394/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-20

USER’S MANUAL

External memories are purchased with guaranteed access times on speed (in nano-

seconds). Table D-16 relates wait states selected by DSACK[3:0] to the memory de-

vice access time.

NOTE

Table D-16 assumes a system configuration that minimizes power

consumption and the number of chip-selects employed. Other ac-

cess techniques can provide the same access times with slower

memory devices, but require more chip-selects to be used and will

subsequently increase system power consumption.

Table D-15 DSACK Field Encoding

DSACK[3:0]

Clock Cycles Required

Per Access

Wait States Inserted

Per Access

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

Fast Termination

1111

—

External DSACK

Table D-16 Memory Access Times at 16.78, 20.97, and 25.17 MHz

Speed

tcyc

Fast Termination Access Time

0 Wait State

1 Wait State

16.78 MHz

62.5 ns

30.0 ns

95.0 ns

155.0 ns

20.97 MHz

50.0 ns

20.0 ns

70.0 ns

120.0 ns

25.17 MHz

40.0 ns

15.0 ns

55.0 ns

95.0 ns

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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