SPMCK16Z4MPV16 datasheet(185/500 Pages) FREESCALE

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M68HC16 Z SERIES

MASKED ROM MODULE

USER’S MANUAL

7-3

Refer to 5.6 Bus Operation for more information concerning access times.

7.5 Low-Power Stop Mode Operation

Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in

MRMCR places the MRM in low-power stop mode. In low-power stop mode, the array

cannot be accessed. The reset state of STOP is the complement of the logic state of

DATA14 during reset. Low-power stop mode is exited by clearing STOP.

7.6 ROM Signature

Signature registers RSIGHI and RSIGLO contain a user-specified mask-programmed

signature pattern. A user-specified signature algorithm provides the capability to verify

ROM array contents.

7.7 Reset

The state of the MRM following reset is determined by the default values programmed

into the MRMCR BOOT, LOCK, ASPC[1:0], and WAIT[1:0] bits. The default array

base address is determined by the values programmed into ROMBAL and ROMBAH.

When the mask programmed value of the MRMCR BOOT bit is zero, the contents of

MRM bootstrap words ROMBS[0:3] are used as reset vectors. When the mask pro-

grammed value of the MRMCR BOOT bit is one, reset vectors are fetched from exter-

nal memory, and system integration module chip-select logic is used to assert the boot

ROM select signal CSBOOT. Refer to 5.9.4 Chip-Select Reset Operation for more

information concerning external boot ROM selection.

Table 7-2 Wait States Field

WAIT[1:0]

Number of

Wait States

Clocks per Transfer

–1

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