ATmega169P datasheet(164/393 Pages) ATMEL

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164

8018N–AVR–08/09

ATmega169P

18.4

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

18-3 and Figure 18-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 18-3 and Table 18-4, as done below:

Figure 18-3. SPI Transfer Format with CPHA = 0

Figure 18-4. SPI Transfer Format with CPHA = 1

Table 18-2.

CPOL Functionality

Leading Edge

Trailing eDge

SPI Mode

CPOL=0, CPHA=0

Sample (Rising)

Setup (Falling)

CPOL=0, CPHA=1

Setup (Rising)

Sample (Falling)

CPOL=1, CPHA=0

Sample (Falling)

Setup (Rising)

CPOL=1, CPHA=1

Setup (Falling)

Sample (Rising)

Bit 1

Bit 6

LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

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