ATMEGA329P_1 datasheet(40/385 Pages) ATMEL

Nome de Peças	ATMEGA329P

Descrição Electrónicos	8-bit Microcontroller with 32K Bytes In-System Programmable Flash

PDF	385 Pages

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Fabricante Electrônico	ATMEL [ATMEL Corporation]

Página de início	http://www.atmel.com

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40 / 385 page

40

8021E–AVR–07/09

ATmega329P/3290P

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 66 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V

CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 209 and ”DIDR0 – Digital

Input Disable Register 0” on page 226 for details.

9.9.7

JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or

Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will

contribute significantly to the total current consumption. There are three alternative ways to

avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or

leaving the JTAG fuse unprogrammed disables the JTAG interface.

Nº de peça semelhante - ATMEGA329P_1

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