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ATMEGA329P Folha de dados(PDF) 38 Page - ATMEL Corporation |
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ATMEGA329P Folha de dados(HTML) 38 Page - ATMEL Corporation |
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38 / 385 page ![]() 38 8021E–AVR–07/09 ATmega329P/3290P USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter- nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 57 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock Sources” on page 28. 9.6 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller interrupt. If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended instead of Power-save mode. The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the LCD controller and Timer/Counter2. 9.7 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 9.8 Power Reduction Register The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 42, pro- vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers inaccessible. Resources used by the peripheral when stopping the clock will remain occupied so the peripheral should be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in IDLE mode and active mode to reduce the overall power con- sumption. In all other sleep modes, the clock is already stopped. |
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