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ATMEGA329P Folha de dados(PDF) 73 Page - ATMEL Corporation |
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ATMEGA329P Folha de dados(HTML) 73 Page - ATMEL Corporation |
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73 / 385 page  73 8021E–AVR–07/09 ATmega329P/3290P low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 68. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 13-7. Overriding Signals for Alternate Functions in PB7:PB4 Signal Name PB7/OC2A/ PCINT15 PB6/OC1B/ PCINT14 PB5/OC1A/ PCINT13 PB4/OC0A/ PCINT12 PUOE 0000 PUOV 0000 DDOE 0000 DDOV 0000 PVOE OC2A ENABLE OC1B ENABLE OC1A ENABLE OC0A ENABLE PVOV OC2A OC1B OC1A OC0A PTOE –––– DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1 DIEOV 1111 DI PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT AIO –––– Table 13-8. Overriding Signals for Alternate Functions in PB3:PB0 Signal Name PB3/MISO/ PCINT11 PB2/MOSI/ PCINT10 PB1/SCK/ PCINT9 PB0/SS/ PCINT8 PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0000 PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0 PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0 PTOE –––– DIEOE PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1 DIEOV 1111 DI PCINT11 INPUT SPI MSTR INPUT PCINT10 INPUT SPI SLAVE INPUT PCINT9 INPUT SCK INPUT PCINT8 INPUT SPI SS AIO –––– |
Nº de peça semelhante - ATMEGA329P_1 |
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Descrição semelhante - ATMEGA329P_1 |
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