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ICS1893 Folha de dados(PDF) 143 Page - Integrated Circuit Systems |
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ICS1893 Folha de dados(HTML) 143 Page - Integrated Circuit Systems |
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143 / 152 page ![]() Chapter 10 DC and AC Operating Conditions ICS1893 Rev C 6/6/00 June, 2000 143 ICS1893 - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.17 Reset: Power-On Reset Table 10-24 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-18 shows the timing diagram for the time periods. Figure 10-18. Power-On Reset Timing Diagram Table 10-24. Power-On Reset Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 VDD ≥ 2.7 V to Reset Complete – 40 45 500 ms TXCLK Valid VDD 2.7 V t1 |
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