M38046FDHKP datasheet(319/387 Pages) RENESAS

319 / 387 page

3-29

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

3.3.3 Notes on interrupts

(1)

Change of relevant register settings

When the setting of the following registers or bits is changed, the interrupt request bit may be set

to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following

sequence.

•Interrupt edge selection register (address 003A16)

•Timer XY mode register (address 002316)

•Timer Z mode register (address 002A16)

•I2C START/STOP condition control register (address 001616)

Set the above listed registers or bits as the following sequence.

Fig. 3.3.1 Sequence of changing relevant register

s Reason

When setting the followings, the interrupt request bit may be set to “1”.

•When setting external interrupt active edge

Concerned register: Interrupt edge selection register (address 003A16)

Timer XY mode register (address 002316)

Timer Z mode register (address 002A16)

I2C START/STOP condition control register (address 001616)

•When switching interrupt sources of an interrupt vector address where two or more interrupt

sources are allocated.

Concerned register: Interrupt source selection register (address 003916)

(2)

Check of interrupt request bit

q When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request

the BBC or BBS instruction.

Set the corresponding interrupt enable bit to “0”

(disabled) .

↓

Set the interrupt edge select bit (active edge switch

bit) or the interrupt (source) select bit to “1”.

↓

NOP (One or more instructions)

↓

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

↓

Set the corresponding interrupt enable bit to “1”

(enabled).

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