H8SLASH3028F datasheet(162/923 Pages) RENESAS

162 / 923 page

Rev. 2.00, 09/03, page 132 of 890

6.3.2

Bus Specifications

The external space bus specifications consist of three elements: (1) bus width, (2) number of

access states, and (3) number of program wait states.

The bus width and number of access states for on-chip memory and registers are fixed, and are not

affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit

bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected

functions as a16-bit access space.

If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-

bit access, 16-bit bus mode is set.

Number of Access States: Two or three access states can be selected with ASTCR. An area for

which two-state access is selected functions as a two-state access space, and an area for which

three-state access is selected functions as a three-state access space.

DRAM space is accessed in four states regardless of the ASTCR settings.

When two-state access space is designated, wait insertion is disabled.

Number of Program Wait States: When three-state access space is designated in ASTCR, the

number of program wait states to be inserted automatically is selected with WCRH and WCRL.

From 0 to 3 program wait states can be selected.

When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1-Tc2 wait) is not inserted.

Also, no program wait is inserted in burst ROM space burst cycles.

Table 6.3 shows the bus specifications for each basic bus interface area.

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