7733 datasheet(263/940 Pages) RENESAS

Nome de Peças	7733

Descrição Electrónicos	16-BIT SINGLE-CHIP MICROCOMPUTER

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SERIAL I/O

7733 Group User’s Manual

8–60

8.4 Clock asynchronous serial I/O (UART) mode

Fig. 8.4.12 Example of receive timing when data is transferred in 8 bits (When parity is disabled and

one stop bit)

RxDi

(Note) RTSi

“1”

“0”

“1”

“H”

“L”

“0”

“1”

Receive enable bit

Start bit

Stop bit

The above timing diagram is applied when

the following conditions are satisfied:

q Parity is disabled.

q 1 stop bit

q RTS function is selected.

→ UARTi receive buffer register

UARTi receive

interrupt request bit

Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software.

Receive completion

flag

Check whether

the level is “L.”

Received data is taken in.

The transfer clock is generated at the

falling edge of start bit, and reception

is started.

BRGi count source

Note: The RTSi output function is not assigned for

Transfer clock

UARTi receive register

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