7733 datasheet(452/940 Pages) RENESAS

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7733 Group User’s Manual

17–45

(2) Initial settings for related registers

17.4 Power saving

Fig. 17.4.1 Initial settings for related registers

Pins KI0

to KI3 are pulled high.

Port P5 direction register (address D 16)

Pins P50 to P53: Output mode

Pins P54 to P57 (KI0 to KI3): Input mode

01 1

1 1

X: It may be “0” or “1.”

Pins P50 to P53’s output (scan output) level: “L”

Port P5 register (address B 16)

00 0 0

Key input interrupt function is selected.

Must be fixed to “0.”

Port function control register (address 6D 16)

Interrupt disable flag (I)

INT2

/Key input interrupt control register (address 7F 16)

Interrupt priority level is set. (Note that a value other than “000 2” is set.)

Interrupt request bit: 0 (Initialized)

Must be fixed to “0.”

“0”: Interrupt is enabled.

Must be fixed to “0.”

An external clock is selected as the main clock.

Watchdog timer is not used when the stop mode is terminated.

Oscillation circuit control register 1 (address 6F 16) (Note)

In the one time PROM version or EPROM version of the 7733 Group,

this bit must be fixed to “1.” (In the 7735 Group, this bit must be fixed to “0.” )

Pin P64/INT2 is not used for the key input interrupt.

Note: When writing a value to this register, write a value of “5516

” by executing theLDM instruction,

and then write a desired value. (Refer to Figure 11.2.4.)

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