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M30620FCAFP Folha de dados(PDF) 302 Page - Renesas Technology Corp

Nome de Peças M30620FCAFP
Descrição Electrónicos  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES
PDF  615 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M30620FCAFP Folha de dados(HTML) 302 Page - Renesas Technology Corp

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Timing
Mitsubishi microcomputers
M16C / 62M Group
(Low voltage version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1-283
Timing requirements
(referenced to VCC = 3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified)
* : Specify a product of -40
°C to 85°C to use it.
Table 1.31.8. External clock input
Table 1.31.9. Memory expansion and microprocessor modes
18
80
60
0
0
80
18
100
0
100
40
40
9
10
(Note)
Note: Calculated according to the BCLK frequency as follows:
tac1(RD – DB) =
f(BCLK) X 2
– 90
[ns]
tac2(RD – DB) =
f(BCLK) X 2
– 90
3 X 10
9
[ns]
tac3(RD – DB) =
f(BCLK) X 2
– 90
3 X 10
9
[ns]
Max.
External clock rise time
ns
tr
Min.
External clock input cycle time
ns
tc
External clock input HIGH pulse width
ns
tw(H)
External clock input LOW pulse width
ns
tw(L)
External clock fall time
ns
tf
Parameter
Symbol
Unit
Standard
Min.
Data input setup time
ns
tsu(DB-RD)
tsu(RDY-BCLK )
Parameter
Symbol
Unit
Max.
Standard
RDY input setup time
ns
Data input hold time
ns
th(RD-DB)
th(BCLK -RDY)
ns
RDY input hold time
HOLD input setup time
ns
tsu(HOLD-BCLK )
HOLD input hold time
ns
th(BCLK-HOLD )
Data input access time (no wait)
ns
tac1(RD-DB)
ns
ns
tac2(RD-DB)
tac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
HLDA output delay time
ns
td(BCLK-HLDA)
(Note)
(Note)



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