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H8SX/1663 Folha de dados(PDF) 305 Page - Renesas Technology Corp

Nome de Peças H8SX/1663
Descrição Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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H8SX/1663 Folha de dados(HTML) 305 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 253 of 1102
REJ09B0294-0100
(2) When DDS = 0
Single address transfer by the DMAC takes place as a full access (normal access). The
DACK
signal is asserted within the Tr cycle and the
BS signal is also asserted during the Tr cycle.
When the DRAM space is accessed with other than the single address transfer by the DMAC, a
fast-page access is available.
Figure 6.59 shows an output timing example of the
DACK signal when DDS = 0.
T
p
T
r
T
c1
T
c2
T
c3
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
DACK
BS
RD/
WR
When DKC = 1
When DKC = 0
Figure 6.59 Output Timing Example of
DACK when DDS = 0 (RAST = 0, CAST = 1)



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