M32CSLASH8B datasheet(222/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 205 of 385

Figure 17.9

IFSR Register

b7 b6 b5 b4

External Interrupt Source Select Register

Symbol

IFSR

Address

031Fh

Bit Symbol

Bit Name

After Reset

00h

Function

IFSR0

0: One edge

1: Both edges

INT0 interrupt polarity

select bit(1)

IFSR1

INT1 interrupt polarity

select bit(1)

0: One edge

1: Both edges

IFSR2

INT2 interrupt polarity

select bit(1)

0: One edge

1: Both edges

IFSR3

INT3 interrupt polarity

select bit(1)

0: One edge

1: Both edges

IFSR4

INT4 interrupt polarity

select bit(1)

0: One edge

1: Both edges

IFSR5

INT5 interrupt polarity

select bit(1)

0: One edge

1: Both edges

IFSR6

UART0, UART3

interrupt source select bit

0: UART3 bus conflict, start condition detection,

stop condition detection

1: UART0 bus conflict, start condition detection,

stop condition detection

IFSR7

UART1, UART4

interrupt source select bit

0: UART4 bus conflict, start condition detection,

stop condition detection

1: UART1 bus conflict, start condition detection,

stop condition detection

NOTE:

1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the

corresponding INTilC register to 0 (falling edge).

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