M16CSLASH29 datasheet(124/499 Pages) RENESAS

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11. DMAC

page 100

11.5 Channel Priority and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de-

tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU

clock), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA

requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC

operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.6

shows an example of DMA transfer effected by external factors.

DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request

are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the

CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is

completed, the bus arbitration is again returned to the CPU.

In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when

DMA requests, as DMA1 in Figure 11.6 occurs more than one time, the DAMS bit is set to 0 as soon

as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.

Figure 11.6 DMA Transfer by External Factors

DMA0

DMA1

DMA0

request bit

DMA1

request bit

CPU

INT0

INT1

Obtainment

of the bus

right

An example where DMA requests for external causes are detected active at the same

CPU clock

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