PSD511B1 datasheet(107/153 Pages) STMICROELECTRONICS

107 / 153 page

PSD5XX Family

104

12.0

System

Configuration

The CSIOP signal, which is generated by the DPLD, selects the internal I/O devices or

registers. The CSIOP signal takes up 256 bytes of address space and is defined by the user

in the PSDSoft Software. The following is an address offset map for the various devices

relative to the CSIOP base address.

Some Motorola 16-bit microcontrollers have a different data bus/data byte orientation. This

requires a different address offset for the internal PSD5XX I/O devices or registers. Tables

30a and 31a in this section are for this group of microcontrollers which include the

M68HC16, M68302 and M683XX.

The following table is the address map offset of the I/O port registers.

Address Offset

Port A

Port B

Port C

Port D

Port E

Data In

Control

Data Out

Direction

Open Drain

Special Function

PLD – I/O

Macrocell Out

Table 30. I/O Register Address Offset

Address Offset

Port A

Port B

Port C

Port D

Port E

Data In

Control

Data Out

Direction

Open Drain

Special Function

PLD – I/O

Macrocell Out

Table 30a. I/O Register Address Offset

(For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 30.)

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