AM261...ZCZQ1 datasheet(132/218 Pages) TI2

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GPMC_CLK

GPMC_CSn[i]

GPMC_A[27:17]

GPMC_BE1n

BPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_WEn

GPMC_WAIT[j]

Address (LSB)

D 0

D 1

D 2

D 3

F15

F17

F18

F20

F14

F22

F21

Address (MSB)

GPMC_AD[15:0]

F14

GPMC_05

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-30. GPMC and Multiplexed NOR Flash — Synchronous Burst Write

6.11.5.7.4 GPMC/NOR Flash Timing Requirements - Asynchronous Mode 100MHz

(7)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FA5(1)

tacc(d)

Data access time

H(5)

FA20(2)

tacc1-pgmode(d)

Page mode successive data access

time

P(4)

FA21(3)

tacc2-pgmode(d)

Page mode first data access time

H(5)

(1)

The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active

functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2)

The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3)

The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4)

P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(5)

H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(6)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(7)

100MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 1 = MAIN_PLL2_HSDIV7_CLKOUT (100/60 MHz)

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

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