IS25LE02GG-RHLA2:P-TY datasheet(169/187 Pages) ISSI

Nome de Peças	IS25LE02GG-RHLA2:P-TY

Descrição Electrónicos	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

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Fabricante Electrônico	ISSI [Integrated Silicon Solution, Inc]

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169 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

169

Rev. A1

10/02/2025

8.68 WRITE VDLR OPERATION (WRVDLR, 4Ah)

Before the Write VDLR (WRVDLR) command can be accepted by the device, a Write Enable (WREN) command

must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded

successfully, the device will set the Write Enable Latch (WEL) to enable the WRVDLR operation.

The WRVDLR command (4Ah) is entered by shifting the instruction and data byte on SI.

CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WRVDLR

command is not executed. As soon as CE# is driven to the logic high state, the WRVDLR operation is initiated

with no delays.

Figure 8.151 WRVDLR Sequence In SPI Mode

Instruction = 4Ah

CE#

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.152 WRVDLR Sequence In QPI Mode

4Ah

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

IS25LE02GG-RHLA2:P-TY Folha de dados(PDF) 169 Page - Integrated Silicon Solution, Inc