IS25LE02GG-RHLA2:P-TY datasheet(154/187 Pages) ISSI

Nome de Peças	IS25LE02GG-RHLA2:P-TY

Descrição Electrónicos	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

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Fabricante Electrônico	ISSI [Integrated Silicon Solution, Inc]

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IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

154

Rev. A1

10/02/2025

8.55 ERASE PPB OPERATION (ERPPB, E4h)

The Erase PPB (ERPPB) command sets all PPB bits to “1”. Before the ERPPB command can be accepted by the

device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable

Latch (WEL) in the Status Register to enable any write operations.

The instruction code is shifted in by the rising edges of the SCK signal. CE# must be driven high after the eighth

bit of the instruction byte has been latched in. This will initiate the beginning of internal erase cycle, which involves

the pre-programming and erase of the entire PPB memory array. Without CE# being driven high after the eighth

bit of the instruction, the PPB erase operation will not be executed.

With the internal erase cycle in progress, the user can read the value of the Write In Progress (WIP) bit to check if

the operation has been completed. The WIP bit will indicate “1” when the erase cycle is in progress and “0” when

the erase cycle has been completed. When the ERPPB operation is completed, the WEL is set to “0”. Erase

suspend is not allowed during PPB Erase.

Figure 8.125 Erase PPB Sequence In SPI Mode

Instruction = E4h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.126 Erase PPB Sequence In QPI Mode

E4h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

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