IS25LE02GG-RHLA2:P-TY datasheet(147/187 Pages) ISSI

Nome de Peças	IS25LE02GG-RHLA2:P-TY

Descrição Electrónicos	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

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Fabricante Electrônico	ISSI [Integrated Silicon Solution, Inc]

Página de início	http://www.issi.com

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IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

147

Rev. A1

10/02/2025

8.51 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h)

FAh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• FAh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• E0h is followed by a 4-byte address (A31-A0)

The instruction is used to read Dynamic Protection Bit (DYB) status of the given sector/block. The instruction code

is entered first, followed by the 24-bit or 32-bit address selecting location zero within the desired sector/block as

above. Then the 8-bit DYB access register contents are shifted out. Each bit (SPI) or four bits (QPI) are shifted out

at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register

continuously by providing multiples of eight bits. The address of the DYB register does not increment so this is not

a means to read the entire DYB array. Each location must be read with a separate Read DYB instruction.

Note: Data must be either 00h (protected) or FFh (unprotected).

Figure 8.111 Read DYB Sequence In SPI Mode (FAh [EXTADD=0], 3-byte address)

Instruction = FAh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

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