IS25LE02GG-RHLA2:P-TY datasheet(119/187 Pages) ISSI

Nome de Peças	IS25LE02GG-RHLA2:P-TY

Descrição Electrónicos	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

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Fabricante Electrônico	ISSI [Integrated Silicon Solution, Inc]

Página de início	http://www.issi.com

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IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

119

Rev. A1

10/02/2025

Figure 8.79 Software Reset Enable and Software Reset Sequence In QPI Mode (RSTEN, 66h + RST, 99h)

66h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

99h

8.39 SECURITY INFORMATION ROW

The security Information Row is comprised of an additional 4 x 512 bytes of programmable information. The security

bits can be reprogrammed by the user. Any program security instruction issued while an erase, program or write

cycle is in progress is rejected without having any effect on the cycle that is in progress.

Table 8.10 Information Row Valid Address Range

Address Assignment

A[23:17]

A[16:9]

A[8:0]

IRL0 (Information Row Lock0)

00h

Byte address

IRL1

00h

08h

Byte address

IRL2

00h

10h

Byte address

IRL3

00h

18h

Byte address

Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.

When Function Register bit IRLx = “0”, the 512 bytes of the programmable memory array can be programmed.

When Function Register bit IRLx = “1”, the 512 bytes of the programmable memory array function as read only.

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