AM263P4 datasheet(125/168 Pages) TI2

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tO20t

O19

OSPI_CLK

OSPI_D[i:0]

Figure 6-34. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback

tO22t

O21

OSPI_DQS

OSPI_D[i:0]

Figure 6-35. OSPI0 Timing Requirements – PHY SDR with External Board Loopback

6.11.5.12.2.2.1.3 OSPI Switching Characteristics - PHY SDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

3.3V

7.5

tw(CLKL)

Pulse duration, OSPI0_CLK low

0.475P(1) - 0.3

tw(CLKH)

Pulse duration, OSPI0_CLK high

0.475P(1) - 0.3

O10

td(CSn-CLK)

Delay time, OSPI0_CSn[1:0] active edge

to OSPI0_CLK rising edge

0.475P(1) + (0.975

× M(2) × R(4)) - 1

0.525P(1) + (1.025

× M(2) × R(4)) + 1

O11

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[1:0] inactive edge

0.475P(1) + (0.975

× N(3) × R(4)) - 1

0.525P(1) + (1.025

× N(3) × R(4)) + 1

O12

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

3.3V

–5.05

–3.36

(1)

P = CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = REFCLK cycle time in ns

tO9t

tO8t

tO7t

tO11t

O12

O10

OSPI_CSn

OSPI_CLK

OSPI_D[i:0]

Figure 6-36. OSPI0 Switching Characteristics – PHY SDR

6.11.5.12.2.2.2 OSPI0 PHY DDR Timing

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AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1

SPRSP81D – OCTOBER 2023 – REVISED MAY 2025

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