Rev. 1.4 March 2007

SODIMM

DDR2 SDRAM

4 of 20

1.0 DDR2 Unbuffered DIMM Ordering Information

2.0 Features

Note :

1. “Z” of Part number(11th digit) stand for Lead-free products.

2. “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Part Number

Density

Organization

Component Composition

Number of Rank

Height

M470T6464AZ3-C(L)E6/D5/CC

512MB

64Mx64

64Mx16 (K4T1G164QA-C(L)E6/D5/CC)*4

1

30mm

M470T2864AZ3-C(L)E6/D5/CC

1GB

128Mx64

64Mx16 (K4T1G164QA-C(L)E6/D5/CC)*8

2

30mm

M470T5669AZ0-C(L)E6/D5/CC

2GB

256Mx64

st.256Mx8 (K4T2G074QA-C(L)E6/D5/CC)*8

2

30mm

• Performance range

• JEDEC standard 1.8V ± 0.1V Power Supply

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination with selectable values(50/75/150 ohms or disable)

• PASR(Partial Array Self Refresh)

• Package: 84ball FBGA - 64Mx16, 70ball FBGA - st.256Mx8

• All of Lead-free products are compliant for RoHS

Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

E6 (DDR2-667)

D5 (DDR2-533)

CC (DDR2-400)

Unit

Speed@CL3

400

400

400

Mbps

Speed@CL4

533

533

400

Mbps

Speed@CL5

667

533

-Mbps

CL-tRCD-tRP

5-5-5

4-4-4

3-3-3

CK

3.0 Address Configuration

Organization

Row Address

Column Address

Bank Address

Auto Precharge

128Mx8(1Gb) based Module

A0-A13

A0-A9

BA0-BA2

A10

64Mx16(1Gb) based Module

A0-A12

A0-A9

BA0-BA2

A10