AT83C5136-RDTUL datasheet(123/171 Pages) ATMEL

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AT83C5134/35/36

7683B–USB–03/07

Table 85. USBINT Register

USBINT (S:BDh)

USB Global Interrupt Register

Reset Value = 00h

WUPCPU

EORINT

SOFINT

SPINT

Bit Number

Bit

Mnemonic Description

7-6

Reserved

The value read from these bits is always 0. Do not set these bits.

WUPCPU

Wake Up CPU Interrupt

This bit is set by hardware when the USB controller is in SUSPEND state and is

re-activated by a non-idle signal FROM USB line (not by an upstream resume).

This triggers a USB interrupt when EWUPCPU is set in Table 86 on page 124.

When receiving this interrupt, user has to enable all USB clock inputs.

This bit will be cleared by software (USB clocks must be enabled before).

EORINT

End Of Reset Interrupt

This bit is set by hardware when a End Of Reset has been detected by the USB

controller. This triggers a USB interrupt when EEORINT is set (see Figure 86 on

page 124).

This bit will be cleared by software.

SOFINT

Start of Frame Interrupt

This bit is set by hardware when an USB Start of Frame PID (SOF) has been

detected. This triggers a USB interrupt when ESOFINT is set (see Table 86 on

page 124).

This bit will be cleared by software.

Reserved

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

SPINT

Suspend Interrupt

This bit is set by hardware when a USB Suspend (Idle bus for three frame

periods: a J state for 3 ms) is detected. This triggers a USB interrupt when

ESPINT is set in see Table 86 on page 124.

This bit will be cleared by software BEFORE any other USB operation to re-

activate the macro.

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