ADC3910CSSS datasheet(118/131 Pages) TI1

Nome de Peças	ADC3910CSSS

Descrição Electrónicos	ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers

PDF	131 Pages

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Fabricante Electrônico	TI1 [Texas Instruments]

Página de início	http://www.ti.com

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7.3 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap

reference powers up and settle out in approximately 2ms.

2. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

3. Begin programming using SPI interface.

7.3.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

• Through a hardware reset or

• By applying a software reset. When using the serial interface, set the RESET bit (register address 0x00) high.

This setting initializes the internal registers to the default values, and then self-resets the RESET bit low. In

this case, the RESET pin is kept low.

After hardware or software reset the wait time is also approximately 200000 clock cycles before the SPI registers

can be programmed.

ADC3910D125

SBASAD1 – DECEMBER 2023

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