CC1110-RTY1 datasheet(120/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 120 of 202

ADCH (0xBB) – ADC Data High

Bit

Name

Reset

R/W

Description

7:0

ADC[13:6]

0x00

Most significant part of ADC conversion result.

ADCCON1 (0xB4) – ADC Control 1

Bit

Name

Reset

R/W

Description

EOC

End of conversion Cleared when both ADCH and ADCL has been

read. If a new conversion is completed before the previous data

has been read, the EOC bit will remain high.

conversion not complete

conversion completed

R/W1

Start conversion. Read as 1 until conversion has completed

no conversion in progress

start a conversion sequence if ADCCON1.STSEL = “11” and

no sequence is running.

5:4

STSEL[1:0]

R/W

Start select. Selects which event that will start a new conversion

sequence.

External trigger on P2_0 pin.

Full speed. Do not wait for triggers.

Timer1 channel1 output = 1

ADCCON1.ST = 1

3:2

RCTRL[1:0]

R/W

Controls the 16 bit random generator. When written “01” or “10”,

the setting will automatically return to “00” when operation has

completed.

Normal operation. (13x unrolling)

Clock the LFSR once (no unrolling).

Seeding from modulator.

NOTE:

The ADC must be running in order for the seeding to start.

Stopped. Random generator is turned off.

1:0

R/W

Reserved. Set to 11.

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