IDT6V31023

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER

IDT®

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER

9

IDT6V31023

REV B 053112

Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics

Electrical Characteristics–PCIe Phase Jitter Parameter

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Duty Cycle

tDC

When driven by 932SQ420 or equivalent

45

49

55

%

1

Duty Cycle Distortion

tDCD

Measured differentially, @100MHz

-2

1

2

%

1,4

Skew, Input to Output

tpdBYP

VT = 50%

2500

3299

4500

ps

1

Additive Jitter

tjcyc-cyc

Cycle to cycle Additive Jitter

1

5

ps

1,3

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR).

For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.

3 Measured from differential waveform

4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

1

2

ps (p-p) 1,2,3,6

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1

0.2

ps

(rms)

1,2,5,6

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.1

0.2

ps

(rms)

1,2,5,6

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.1

0.2

ps

(rms)

1,2,4,5,

6

1 Applies to all outputs.

5 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]

6 Applies to 100MHz spread off and 0.5% down spread sources only.

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

4 Subject to final radification by PCI SIG.

2 See http://www.pcisig.com for complete specs

tjphPCIeG2

Additive Phase Jitter

33

HCSL Output

33

50

50

HCSL Differential Output Test Load

2pF

2pF

Zo=100ohm differential