2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

2

OCTOBER 18, 2016

9FGU0231 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

24 23 22 21 20 19

XIN/CLKIN_25 1

18 DIF1#

X2 2

17 DIF1

VDDXTAL1.5 3

16 VDDA1.5

vSADR/REF1.5 4

15 GNDA

GNDREF 5

14 DIF0#

GNDDIG 613 DIF0

78

9 10 11 12

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

v prefix indicates internal 120KOhm pull down resistor

9FGU0231

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

True O/P

Comp. O/P

0

X

Low

Low

Hi-Z1

1

1

Running

Running

Running

1

0

Low

Low

Low

CKPWRGD_PD#

SMBus

OE bit

1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,

when CKPWRG_PD# is low, REF is Low.

DIFx

REF

Pin Number

VDD

GND

35,24

76

11,20

10,21

16

15

PLL Analog

Description

XTAL, REF

Digital

DIF outputs