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HC705JJ7GRS/D Folha de dados(PDF) 218 Page - NXP Semiconductors

Nome de Peças HC705JJ7GRS/D
Descrição Electrónicos  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
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HC705JJ7GRS/D Folha de dados(HTML) 218 Page - NXP Semiconductors

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Electrical Specifications
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications
15.17 Reset Characteristics
Figure 15-2. Stop Recovery Timing Diagram
Characteristic
Symbol
Min
Typ
Max
Unit
Low-Voltage Reset
Rising Recovery Voltage
Falling Reset Voltage
LVR Hysteresis
VLVRR
VLVRF
VLVRH
2.4
2.3
100
3.4
3.3
—
4.4
4.3
—
V
V
mV
POR Recovery Voltage (see Note 2)
VPOR
0
—
100
mV
POR VDD Slew Rate (see Note 2)
Rising (see Note 2)
Falling (see Note 2)
SVDDR
SVDDF
—
—
—
—
0.1
0.05
V/
µs
RESET Pulse Width (when Bus Clock Active)
tRL
1.5
—
—
tCYC
RESET Pulldown Pulse Width
(from Internal Reset)
tRPD
3—4
tCYC
NOTE:
1.
+2.7
≤ V
DD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2.
By design, not tested
PCH
NEW
1FFE
t
RL
OSC1
1
RESET
Internal
Clock3
Internal
Address
Bus3
4064 or 16 t
cyc
2
NOTES:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064 tCYC or short delay option of 16 tCYC
3. Internal timing signal and data information not available externally
Internal
Data
Bus3
1FFF
NEW PCH
NEW PCL
PCL
NEW
code
Op
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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