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TPS7H1111MPWPTSEP Folha de dados(PDF) 9 Page - Texas Instruments |
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TPS7H1111MPWPTSEP Folha de dados(HTML) 9 Page - Texas Instruments |
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9 / 59 page ![]() 7.3 Recommended Operating Conditions over operating temperature range, TJ = –55°C to 125°C (unless otherwise noted) MIN NOM MAX UNIT Input voltage IN 0.85 7 V BIAS(1) VIN VOUT + 1.6 V 2.2 14 PG 0 7 EN 0 7 FB_PG 0 6 CLM 0 VIN Output voltage OUT(2) VIN – VDO V 0.4 5.5 SS_SET(2) VIN – VDO 0.4 5.5 Input current PG 0 0.002 A Output current OUT 0 1.5 A Output bulk capacitance (3) COUT 132 200 308 µF ESR 7 40 mΩ ESL 0.8 2.4 nH Reference configuration RREF 11 12 13 kΩ EN toggle time(4) tEN_LOW 20 µs Junction temperature TJ –55 125 °C (1) BIAS has two minimum values, VIN and 2.2 V. BIAS must be set greater than or equal to the larger of these two values. The BIAS max value is always 14 V. For full performance set VBIAS ≥ VOUT + 1.6 V. See the Bias Supply Section for further details. (2) OUT and SS_SET have two maximum values, (VIN – VDO) and 5.5 V. OUT and SS_SET must be set to less than or equal to the smaller of these two values. The OUT and SS_SET min value is always 0.4 V. (3) These are the default acceptable output capacitance, equivalent series resistance (ESR), and equivalent series inductance (ESL) values for the bulk capacitance. Other values may be acceptable, such as by modifying the control loop with external compensation using the STAB pin. Tantalum or Tantalum Polymer capacitors are normally used to meet these requirements. Additional ceramic decoupling capacitors are not required, but a single 0.1 µF ceramic capacitor with low ESL near the point of load is acceptable. Additional larger ceramic capacitors are not needed due to the high PSRR and low noise provided by the TPS7H1111 LDO across a wide bandwidth. Therefore, the TPS7H1111 is not designed to support larger ceramic capacitors. See the Output Capacitance Section for additional information. (4) tEN_LOW is the time the EN pin must be driven low before again being driven high for the device to detect a reset. This is generally only applicable when attempting to exit turn-off current limit mode. 7.4 Thermal Information THERMAL METRIC(1) TPS7H1111-SP TPS7H1111-SP, -SEP UNIT CFP HBL PWP (HTSSOP) 14 PINS 28 PINS RθJA Junction-to-ambient thermal resistance 25.1 24.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 6.3 15.6 °C/W RθJB Junction-to-board thermal resistance 9.3 6.6 °C/W ΨJT Junction-to-top characterization parameter 1.4 0.2 °C/W ΨJB Junction-to-board characterization parameter 9.1 6.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 1.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TPS7H1111-SP SLVSFT8 – FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS7H1111-SP |
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