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TPS7H1111MPWPTSEP Folha de dados(PDF) 4 Page - Texas Instruments |
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TPS7H1111MPWPTSEP Folha de dados(HTML) 4 Page - Texas Instruments |
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4 / 59 page  6 Pin Configuration and Functions HBL Package PWP Package 14-Pin CFP 28-Pin HTSSOP Top View Top View BIAS EN IN IN CLM GND PG FB_PG OUTS OUT OUT STAB SS_SET REF Thermal Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BIAS EN IN IN CLM GND PG FB_PG OUTS OUT OUT STAB SS_SET REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IN GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OUT Thermal Pad NC NC NC NC NC NC NC NC NC NC NC Pin Functions PIN I/O (1) DESCRIPTION NAME HBL (14) NO. PWP (28) NO. BIAS 1 3 I Bias supply. To support full output current, a separate bias supply is required if the headroom voltage is less than 1.6 V (Vheadroom = VIN – VOUT < 1.6 V). Set the separate bias supply to a voltage at least 1.6 V higher than VOUT for full output current support. A 12 V bias supply will satisfy these conditions (generally a 5 V supply will also suffice). There are no sequencing requirements between VBIAS and VIN. In order to limit noise on BIAS, an RC filter is recommended (typically 10 Ω and 4.7 μF) unless VBIAS is an ultra-clean supply. If a separate bias supply is not used, connect BIAS to VIN (it is also recommended to connect the VIN rail to the BIAS pin through an RC filter). EN 2 4 I Enable. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. If enable functionality is not required, connect this pin to IN. Do not float this pin. IN 3, 4 6, 7, 8 I Input power. An input capacitor (nominally 10 μF) near this pin is recommended. CLM 5 9 I Current limit mode. Connect CLM to VIN for brick-wall current limit mode (when current limit is reached, VOUT is regulated to maintain a constant output current until the fault is removed). Connect CLM to GND for turn-off current limit mode (when current limit is reached, VOUT stops regulating until EN is toggled). Do not change the value of this pin when the device is enabled, and do not float this pin. GND 6 10, 11 — Ground PG 7 12 O Power good indicator. This is an open drain pin. Use a pull-up resistor to pull this pin up to VOUT or the desired logic level. It is recommended to pull down PG to ground if unused but it may be left floating. REF 8 18 I/O Reference pin. REF outputs a nominal 1.2 V. Place a high accuracy 12.0 kΩ external resistor from REF to GND to set the internal 100 μA current source. SS_SET 9 19 I/O Soft-start and voltage set pin. An external capacitor (nominally 4.7 μF ceramic) is used to slow down the output voltage ramp rate during startup along with filtering internal device noise. Capacitor values less than 4.7 μF will result in marginally higher output noise. There is internal fast start circuitry to enable reasonable soft start times. Additionally, a resistor from SS_SET to GND sets the output voltage. During nominal operation, 100 μA is output on this pin and a resistor from SS_SET to GND sets the output voltage. STAB 10 20 I/O Stability pin. This is an output from the internal OTA (operational transconductance) error amplifier to aid in measuring or optimizing the control loop. Use a series capacitor (CCOMP) and resistor (RCOMP) of 4.7 nF and 5 kΩ to compensate the device. For different compensation options, view Section 9.3.8.2. A C0G (NP0) type capacitor capable of withstanding the lower of VBIAS or 7.5 V is recommended (for example, a 25 V rated capacitor). TPS7H1111-SP SLVSFT8 – FEBRUARY 2023 www.ti.com 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS7H1111-SP |
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