DRA821U4...ALM datasheet(145/252 Pages) TI

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7.9.5 Peripherals

7.9.5.1 ATL

The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL

calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock

using cycle stealing via software.

Note

For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the

device TRM.

Table 7-25 represents ATL timing conditions.

Table 7-25. ATL Timing Conditions

PARAMETER

MODE

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

External reference CLK

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

Internal reference CLK

Section 7.9.5.1.1, Section 7.9.5.1.2, Section 7.9.5.1.3, and Section 7.9.5.1.4 present timing requirements and

switching characteristics for ATL.

7.9.5.1.1 ATL_PCLK Timing Requirements

NO.

PARAMETER

MODE

MIN

MAX UNIT

tc(pclk)

Cycle time, ATL_PCLK

External reference

CLK

tw(pclkL)

Pulse Duration, ATL_PCLK low

External reference

CLK

0.45 × M

(1) + 2.5

tw(pclkH)

Pulse Duration, ATL_PCLK high

External reference

CLK

0.45 × M

(1) + 2.5

(1)

M = ATL_CLK[x] period

7.9.5.1.2 ATL_AWS[x] Timing Requirements

NO.

MODE

MIN

MAX UNIT

tc(aws)

Cycle Time, ATL_AWS[x](3)

External reference

CLK

2 × M(1)

tw(awsL)

Pulse Duration, ATL_AWS[x](3) low

External reference

CLK

0.45 × A(2) + 2.5

tw(awsH)

Pulse Duration, ATL_AWS[x](3) high

External reference

CLK

0.45 × A(2) + 2.5

(1)

M = ATL_CLK[x] period

(2)

A = ATL_AWS[x] period

(3)

x = 0 to 3

7.9.5.1.3 ATL_BWS[x] Timing Requirements

NO.

MODE

MIN

MAX UNIT

tc(bws)

Cycle Time, ATL_BWS[x](3)

External reference

clock

2 × M(1)

tw(bwsL)

Pulse Duration, ATL_BWS[x] low(3)

External reference

clock

0.45 × B(2) + 2.5

www.ti.com

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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