AM652X datasheet(257/284 Pages) TI

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The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN

FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices

can coexist on the same network without any conflict.

The device supports two MCAN modules - MCU_MCAN0 and MCU_MCAN1. They connect to the physical layer

of the CAN network through external (for the device) transceivers. Each MCAN module supports flexible bit rates

greater than 1 Mbps and is compliant to ISO 11898-1:2015.

For more information, see Modular Controller Area Network (MCAN) section in the device TRM.

8.4.5.17 MCASP

The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio

applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for

time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for

an intercomponent digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly connect

to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.

Although intercomponent digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not

natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows

an easy connection to external DIR components (for example, S/PDIF to I2S format converters).

For more information, see Multichannel Audio Serial Port (MCASP) section in the device TRM.

8.4.5.18 MCRC

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the

integrity of a memory system. A signature representing the contents of the memory is obtained when the

contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate

the signature for a set of data and then compare the calculated signature value against a predetermined good

signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in

parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC

controller compresses each data being read through CPU read data bus.

For more information, see Memory Cyclic Redundancy Check (MCRC) Controller section in the device TRM.

8.4.5.19 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.

There are total of eight MCSPI modules in the device.

MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:

• MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and MCSPI3

may be optionally mapped to external device pads.

• MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and

MCU_MCSPI2 are not pinned out externally.

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in the device TRM.

8.4.5.20 MMCSD

There are two MMCSD modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module includes

one MMCSD Host Controller.

Each controller has the following data bus width:

• MMCSD0 - 8-bit wide data bus

• MMCSD1 - 4-bit wide data bus

The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure

Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMCSD/SDIO

protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,

and checking for syntactical correctness.

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AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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Product Folder Links: AM6548 AM6528 AM6546 AM6526

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