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STM32G474VC Folha de dados(PDF) 200 Page - STMicroelectronics

Nome de Peças STM32G474VC
Descrição Electrónicos  Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
PDF  236 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474VC Folha de dados(HTML) 200 Page - STMicroelectronics

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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
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DS12288 Rev 4
Figure 52. Quad SPI timing diagram - SDR mode
tw(CKH) Quad SPI clock high
and low time
Even division
PRESCALER [7:0]
n =0,1, 3, 5 ...
t(CK)/2
-
t(CK)/2+1
ns
tw(CKL)
t(CK)/2-1
-
t(CK)/2
tw(CKH) Quad SPI clock high and
low time
Odd division
PRESCALER [7:0]
n =2,4, 6, 8...
(n/2)*t(CK)/(n+1)
-
(n/2)*t(CK)/(n+1) + 1
tw(CKL)
(n/2+1)*t(CK)/(n+1) - 1
-
(n/2+1)*t(CK)/(n+1)
tsr(IN)
Data input setup time on
rising edge
1.71 < VDD< 3.6 V
1
-
-
tsf(IN)
Data input setup time on
falling edge
1.71 < VDD< 3.6 V
1
-
-
thr(IN)
Data input hold time on
rising edge
1.71 < VDD< 3.6 V
6
-
-
thf(IN)
Data input hold time on
falling edge
1.71 < VDD< 3.6 V
5
-
-
tvr(OUT)
Data output valid time on
rising edge
1.71 < VDD< 3.6 V
DHHC = 0
-
7.5
8
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+1.5
tvf(OUT) Data output valid time
1.71 < VDD< 3.6 V
DHHC = 0
-
710
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+2
thr(OUT)
Data output hold time on
rising edge
1.71 < VDD< 3.6 V
DHHC = 0
2-
-
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+ 0.5
-
-
thf(OUT)
Data output hold time on
falling edge
1.71 < VDD< 3.6 V
DHHC = 0
3-
-
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+0.5
-
-
1. Guaranteed by characterization results.
Table 109. QUADSPI characteristics in DDR mode(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv36878V1
Data output
D0
D1
D2
Clock
Data input
D0
D1
D2
t(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
ts(IN)
th(IN)
tv(OUT)
th(OUT)



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