DS31256 datasheet(154/183 Pages) MAXIM

Nome de Peças	DS31256

Descrição Electrónicos	256-Channel, High-Throughput HDLC Controller

PDF	183 Pages

Scroll/Zoom	100%

Fabricante Electrônico	MAXIM [Maxim Integrated Products]

Página de início	https://www.maximintegrated.com/en.html

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154 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

154 of 183

Bit 6/Local Bus Width (LBW)

0 = 16 bits

1 = 8 bits

Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four bits determine the total time the

local bus seizes the bus when it has been granted in the arbitration mode (LARBE = 1). This period is measured

from LHLDA (

LBG) being detected to LBGACK inactive.

CONDITION

33MHz PCLK

25MHz PCLK

0000 = when granted, hold the bus for 32 LCLKs

0.97

µs

1.3

µs

0001 = when granted, hold the bus for 64 LCLKs

1.9

µs

2.6

µs

0010 = when granted, hold the bus for 128 LCLKs

3.9

µs

5.1

µs

0011 = when granted, hold the bus for 256 LCLKs

7.8

µs

10.2

µs

0100 = when granted, hold the bus for 512 LCLKs

15.5

µs

20.5

µs

1101 = when granted, hold the bus for 262,144 LCLKs

7.9ms

10.5ms

1110 = when granted, hold the bus for 524,288 LCLKs

15.9ms

21.0ms

1111 = when granted, hold the bus for 1,048,576 LCLKs

31.8ms

41.9ms

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