AM652X datasheet(248/282 Pages) TI

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8.2 Processor Subsystems

8.2.1 Arm Cortex-A53

The SoC implements two Dual-Core Arm Cortex-A53 Subsystems (CC_ARMSS0 and CC_ARMSS1), which

are both integrated inside the Compute Cluster (along with the MSMC module). The Cortex-A53 cores are

general-purpose processors that can be used for running customer applications.

The CC_ARMSS is built around the Cortex-A53 MPCore (Arm A53 Cluster), which is provided by Arm and

configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high

performance and optimal power management, debug and emulation capabilities.

The A53 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 Instruction

and Data Caches, compatible with Arm®v8-A architecture. It delivers significantly more performance than its

predecessors at a higher level of power efficiency.

For more information, see Compute Cluster Arm Cortex-A53 Subsystem section in the device TRM.

8.2.2 Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm Cortex-R5F processor configured for split/lock

operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®

CoreSight® debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and

various other modules for protocol conversion and address translation for easy integration into the SoC.

For more information, see MCU Arm Cortex-R5F Subsystem section in the device TRM.

AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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AM652X Folha de dados(PDF) 248 Page - Texas Instruments