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7.9.5.18 OSPI

For more details about features and additional description information on the device Octal Serial Peripheral

Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed

Description.

Table 7-66 presents timing conditions for OSPI.

Table 7-66. OSPI Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

All modes

V/ns

OUTPUT CONDITIONS

Output load capacitance

All modes

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay

OSPI_CLK trace

Internal Loopback;

Internal Pad Loopback

450

Propagation delay

OSPI_LBCLKO trace

External Board Loopback

2*L(2)-30

2*L(2)+30

Propagation delay

OSPI_DQS trace

DQS

L(2)-30

L(2)+30

td(Trace Mismatch

Delay)

Propagation delay mismatch

OSPI_D[i:0](1), OSPI_CSn

relative to OSPI_CLK

All modes

(1)

i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1

(2)

L = Propagation delay of OSPI_CLK trace

7.9.5.18.1 OSPI with Data Training

Note

I/O timing requirements and switching characteristics are not applicable when OSPI is used with data

training. Follow the Section 9.2.2, OSPI and QSPI Board Design and Layout Guidelines to ensure

proper operation.

7.9.5.18.1.1 OSPI Switching Characteristics - Data Training

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V, SDR

5.00

3.3V, SDR

7.52

1.8V, DDR

6.02

3.3V, DDR

7.52

7.9.5.18.2 OSPI without Data Training

Note

The I/O Timings provided in this section are only applicable when data training is not implemented.

Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL

Delays are configured as described in Table 7-67 found in this section.

Section 7.9.5.18.2.4, Section 7.9.5.18.2.2, Figure 7-90, and Figure 7-88 present switching characteristics for

OSPI DDR and SDR Mode.

AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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