AM652X datasheet(224/277 Pages) TI1

224 / 277 page

GPO[n:0]

PRDO1

SPRS91x_TIMING_PRU_02

224

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

5.9.5.20 PCIE

The PCI-Express Subsystem is compliant with the PCI Express Base Specification, revision 3.1. Refer to

the specification for timing details.

For more details about features and additional description information on the device Peripheral

Component Interconnect Express, see the corresponding sections within Section 4.3, Signal Descriptions

and Section 6, Detailed Description.

5.9.5.21 PRU_ICSSG

The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and

PRU_ICSSG2). The programmable nature of the PRU cores, along with their access to pins, events and

all device resources, provides flexibility in implementing fast real-time responses, specialized data

handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores

of the device.

For more details about features and additional description information on the device Programmable Real-

Time Unit Subsystem and Industrial Communication Subsystem - Gigabit, see the corresponding sections

within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

5.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)

NOTE

The PRU_ICSSG PRU signals have different functionality depending on the mode of

operation. The signal naming in this section matches the naming used in the PRU Module

Interface section in the device TRM.

5.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing

(1) m in GPI[m:0] = 19.

Table 5-90. PRU_ICSSG PRU Switching Characteristics - Direct Output Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRDO1

tsk(PRU_DATAOUT)

PRU_DATAOUT skew

Figure 5-94. PRU_ICSSG PRU Direct Output Timing

(1) n in GPO[n:0] = 19.

5.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing

Table 5-91. PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRPC1

tc(PRU_CLOCK)

Cycle time, PRU_CLOCK

PRPC2

tw(PRU_CLOCKL)

Pulse Duration, PRU_CLOCK Low

PRPC3

tw(PRU_CLOCKH)

Pulse Duration, PRU_CLOCK High

PRPC4

tsu(PRU_DATAIN-

PRU_CLOCK)

Setup time, PRU_DATAIN valid before PRU_CLOCK active edge

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