AM652X datasheet(192/277 Pages) TI1

192 / 277 page

GPMC_FCLK

GPMC_CSn[x]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_WEn

DATA

GNF0

GNF1

GNF4

GNF9

GNF3

GNF6

GPMC_AD[15:0]

GPMC_15

GPMC_CSn[x]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_FCLK

GPMC_WAIT[x]

GNF10

GNF14

GNF15

GNF12

GNF13

DATA

GPMC_AD[15:0]

GPMC_14

192

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(1)

GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active

functional clock edge. GNF12 value must be stored inside AccessTime register bits field.

(2)

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3)

In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

Figure 5-57. GPMC and NAND Flash—Data Read Cycle

(1)

In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

Figure 5-58. GPMC and NAND Flash—Data Write Cycle

For more information, see section General-Purpose Memory Controller (GPMC) in the device TRM.

5.9.5.11 HyperBus

For more details about features and additional description information on the device Hyperbus, see the

corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

Table 5-58, Table 5-59, and Table 5-60 assume testing over the recommended operating conditions and

electrical characteristic conditions (see Figure 5-59, Figure 5-60, and Figure 5-61).

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