AM652X datasheet(241/299 Pages) TI1

241 / 299 page

241

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Dual Arm Cortex-R5F CPU configuration

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Revision r1p3

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Armv7-R profile

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Split/Lock operation

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Split mode: Two independently operating cores (Asymetric Multi Processing, no coherence)

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Lock (lockstep) mode: One main operating core with the other operating in lockstep for safety

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Boot-time configurable to be in split or lock mode

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L1 Memory System

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16KB Instruction Cache

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4x4KB ways

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SECDED ECC protected per 64 bits

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16KB Data Cache

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4x4KB ways

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SECDED ECC protected per 32 bits

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64KB Tightly-Coupled Memory (TCM) per CPU

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SECDED ECC protected per 32 bits

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Readable/Writable from system

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Split into A and B banks (with B further splitting into B0 and B1 interleaved banks)

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32KB TCMA (ATCM)

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16KB TCMB0 (B0TCM)

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16KB TCMB1 (B1TCM)

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Low interrupt latency with restartable instructions

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Non-Maskable Interrupt (NMI)

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Full-Precision Floating Point (VFPv3)

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16-Region Memory Protection Unit (MPU)

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8 Breakpoints

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8 Watchpoints

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Dynamic Branch Prediction with Global History Buffer and 4-entry Return Stack

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CoreSight Debug Access Port (DAP)

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CoreSight ETM-R5 Interface

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Performance Monitoring Unit (PMU)

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Interfaces

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64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses (per core)

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64-bit VBUSM slave for TCM access (per core)

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Also allows access to cache for debug purposes

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32-bit VBUSP master for peripheral access (per core)

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32-bit VBUSP slave config port (per core)

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32-bit VBUSP slave debug port

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Allows access to all MCU_ARMSS internal debug logic

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32-bit to 48-bit Region-based Address Translation (RAT) on memory access masters

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16 Regions

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Synchronous clock domain crossing on all interfaces

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