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Os motores de busca de Datasheet de Componentes eletrônicos |
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AM652X Folha de dados(PDF) 203 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 203 Page - Texas Instruments |
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203 / 299 page  MMC0 CLK _ MMC0 CMD _ MMC0 DAT[7:0] _ DDR1 DDR2H DDR2L DDR3 DDR4 DDR7 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 SPRSP08_MMC0_05 MMC0_CLK MMC0_CMD MMC0_DAT[7:0] JC641 JC642L JC645 JC645 JC646 JC646 mmc0_04 JC642H 203 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-72. MMC0 SD Card Interface - JC64 High Speed SDR Transmitter Mode Table 5-68 and Table 5-69 present Timing requirements and Switching characteristics for MMC0 - JC64 High speed DDR in receiver and transmitter mode (see Figure 5-73 and Figure 5-74). Table 5-68. Timing Requirements for MMC0 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR3 tsu(cmdV-clk) Setup time, MMC0_CMD valid before MMC0_CLK transition Positive-edge Reference Clock 6.21 ns DDR4 th(clk-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK transition Positive-edge Reference Clock 2.83 ns DDR7 tsu(dV-clk) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition Both-edge Reference Clock 1.16 ns DDR8 th(clk-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition Both-edge Reference Clock 1.67 ns Figure 5-73. MMC0 SD Card Interface - JC64 High Speed DDR Receiver Mode Table 5-69. Switching Characteristics for MMC0 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR1 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock 48 MHz DDR2H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.82 (1) ns DDR2L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.82 (1) ns DDR5 td(clk-cmdV) Delay time, MMC0_CLK transition to MMC0_CMD transition Negative-edge Reference Clock -6.5 6.5 ns DDR6 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition Both-edge Reference Clock 3.42 7 ns |
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